1 tm file number 4607.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. satellite applications flow (saf) is a trademark of intersil corporation. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 HS-565ARH-T radiation hardened high speed, monolithic digital-to-analog converter intersil s satellite applications flow tm (saf) devices are fully tested and guaranteed to 100 krad total dose. this qml class t device is processed to a standard ?w intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the HS-565ARH-T is a fast, radiation hardened 12-bit current output, digital-to-analog converter. the monolithic chip includes a precision voltage reference, thin-?m r-2r ladder, reference control ampli?r and twelve high-speed bipolar current switches. the intersil semiconductor dielectric isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code- dependent ground currents. HS-565ARH-T die are laser trimmed for a maximum integral nonlinearity error of 0.25 lsb at 25 o c. in addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient. speci?ations speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed below must be used when ordering. detailed electrical speci?ations for the HS-565ARH-T are contained in smd 5962-96755. a ?ot-link?is provided from our website for downloading . www.intersil.com/spacedefense/newsafclasst.asp intersil? quality management plan (qm plan), listing all class t screening operations, is also available on our website. www.intersil.com/quality/manuals.asp features qml class t, per mil-prf-38535 radiation performance - gamma dose ( ) 1 x 10 5 rad (si) - no latch-up, dielectrically isolated device islands dac and reference on a single chip pin compatible with ad-565a and hi-565a very high speed: settles to 0.50 lsb in 500ns max monotonicity guaranteed over temperature 0.50 lsb max nonlinearity guaranteed over temperature low gain drift (max., dac plus reference) 50ppm/ o c 0.75 lsb accuracy guaranteed over temperature ( 0.125 lsb typical at 25 o c) pinouts hs1-565arh-t (sbdip), cdip2-t24 top view hs9-565arh-t (flatpack), cdfp4-f24 top view ordering information ordering number part number temp. range ( o c) 5962r9675501tjc hs1-565arh-t -55 to 125 5962r9675501txc hs9-565arh-t -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 nc nc v cc ref out ref gnd ref in -v ee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in (msb) bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in (lsb) bit 2 in bit 7 in bit 9 in 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 nc nc v cc ref out ref gnd ref in -v ee bipolar rin idac out 10v span 20v span pwr gnd bit 1 in bit 3 in bit 4 in bit 5 in bit 6 in bit 8 in bit 10 in bit 11 in bit 12 in bit 2 in bit 7 in bit 9 in (lsb) (msb) data sheet november 2000
2 functional diagram de?itions of speci?ations digital inputs the HS-565ARH-T accepts digital input codes in binary format and may be user connected for any one of three binary codes. straight binary, two s complement (see note below), or offset binary (see operating instructions). accuracy nonlinearity - nonlinearity of a d/a converter is an important measure of its accuracy. it describes the deviation from an ideal straight line transfer curve drawn between zero (all bits off) and full scale (all bits on). differential nonlinearity - for a d/a converter, it is the difference between the actual output voltage change and the ideal (1 lsb) voltage change for a one bit change in code. a differential nonlinearity of 1 lsb or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. settling time settling time is the time required for the output to settle to within the speci?d error band for any input code transition. it is usually speci?d for a full scale or major carry transition, settling to within 0.50 lsb of ?al value. drift gain drift - the change in full scale analog output over the speci?d temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). gain error is measured with respect to 25 o c at high (t h ) and low (t l ) temperatures. gain drift is calculated for both high (t l - 25 o c) and low ranges (25 o c - t l ) by dividing the gain error by the respective change in temperature. the speci?ation is the larger of the two representing worst case drift. offset drift - the change in analog output with all bits off over the speci?d temperature range expressed in parts per million of full scale range per o c (ppm of fsr/ o c). offset error is measured with respect to 25 o c at high (t h ) and low (t l ) temperatures. offset drift is calculated for both high (t d - 25 o c) and low (25 o c-t l ) ranges by dividing the offset error by the respective change in temperature. the speci?ation given is the larger of the two, representing worst case drift. power supply sensitivity power supply sensitivity is a measure of the change in gain and offset of the d/a converter resulting from a change in -15v or +15v supplies. it is specified under dc conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of fsr/%). compliance compliance voltage is the maximum output voltage range that can be tolerated and still maintain its speci?d accuracy. compliance limit implies functional operation only and makes no claims to accuracy. glitch a glitch on the output of a d/a converter is a transient spike resulting from unequal internal on-off switching times. worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. for example, if turn on is greater than turn off for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. matched switching times and fast switching will reduce glitches considerably. ref out v cc 43 + - 19.95k ref 10v 6 5 ref + - 3.5k 3k i ref 0.5ma -v ee pwr gnd 712 24. . . 13 msb lsb (4x iref x code) gnd in 20v span 10v span out io dac 9.95k bip. off. 8 5k 5k 2.5k 11 10 9 digital input analog output straight binary offset binary (note) two? complement msb . lsb 000 . . . 000 zero - f s (full scale) zero 100 . . . 000 0.50 f s zero - f s 111 . . . 111 + f s - 1 lsb + f s - 1 lsb zero - 1 lsb 011 . . . 111 0.50 f s - 1 lsb zero - 1 lsb + f s - 1 lsb note: invert msb with external inverter to obtain two s complement coding. HS-565ARH-T
3 applying the HS-565ARH-T op amp selection the HS-565ARH-T |